1. Field of the Invention
The present invention relates to a semiconductor memory device, having at least one, normally a plurality, of memory cells. It also relates to a method of operating such a semiconductor memory device.
2. Summary of the Prior Art
In a semiconductor memory device, such as a DRAM or SRAM, a plurality of memory cells are provided, each having a switching element and a capacitive element connected to the switching element. Peripheral control circuits control the voltage across the connected switching element and capacitive element, and also control the signal to a control terminal of the switching element, to permit data to be stored in the respective memory cells by suitable storage of charge in each capacitive elements. The capacitive elements are controlled so that they define logical "1" and logical states, and thus the memory device, as a whole, can store data in the form of logical signals in each of the memory cells.
In U.S. Pat. No. 4,873,664 it was proposed the capacitive element of such a memory device be in the form of a ferroelectric capacitive element. Such an element may be polarised in different directions, and exhibits a hysteresis effect in the change from one polarisation to another. Thus, if the ferroelectric capacitive element is in one polarisation state, it may be changed to another polarisation state by application of a suitable voltage. However, when that voltage is removed, the polarisation will not change back to the first state, but will remain in the second state. In order to change back to the first state, a suitable voltage in an opposite direction must be applied. Thus, the use of ferroelectric capacitive elements in memory cells of a memory device gives the advantage that the data stored by the memory is not lost even when power is removed from the memory device.
In U.S. Pat. No. 4,914,627, the idea of U.S. Pat. No. 4,873,664 was developed further, by providing two ferroelectric capacitive elements in each memory cell. The two ferroelectric capacitive elements were connected in common to a terminal of the switching element of the memory cell. In U.S. Pat. No. 4,914,627, it was proposed that the same data be written in to each of the two ferroelectric capacitive elements of the memory cell, and then the data read out separately.